The present invention relates to forming inductors in indicated circuits, and in particular to isolating such inductors from the substrate to improve the quality factor and insensitivity to noise.
A monolithic inductor can be implemented with a standard CMOS manufacturing process by employing coils on one or more metal layers in a series or parallel configuration. These coils can be square, octagonal or an approximately circular shape within the limits of the minimum feature size in the patterning lithography used. Thicker than usual metal layers or the connection of multiple parallel metal layers can be used to reduce the series resistance of the inductor in order to make it appear closer to an ideal inductive element. In order to reduce the total capacitance within the inductor loops, and from the inductor to the substrate, a number of inner metal loops can be removed to create a center core opening, which increases the self-resonance frequency (which is the frequency above which the device reactance is dominated by the capacitance).
Quality factor (Q) is an important figure of merit for the inductor in circuit applications. Q measures how closely the inductor behaves to an ideal inductive element. Quality factor is defined from the ratio of the stored energy in the electromagnetic field of the device versus the dissipated power in the device per unit time as shown in Equation 1.Q=ω·EtotPave=ω·(½·1pk2R).  Equation 1
Hence the quality factor of the inductor can be determined from the ratio of the inductive reactance to series resistance at a specific frequency, as in Equation 2 when the reduction in Q due to self-resonance or substrate losses are not included.Q=ω·L/R, where  Equation 2
L is inductance value, R is series resistance value, ω=2πf and f is the signal frequency.
A monolithic inductor is susceptible to noise from surrounding circuit elements. These circuit elements can couple to the inductor voltage and current via the electromagnetic field that is induced by the inductor. Coupling can be either capacitive via parasitic device capacitances or inductive from magnetic field coupling. The substrate under the inductor is the only circuit feature that cannot be moved further away from the metal layers of the inductor by design optimization, and hence it presents the dominant contributor to the noise that is coupled to the inductor. Noise in the substrate is generated by any other circuit element that is fabricated on the same substrate.
A standard CMOS process employs a relatively low resistivity substrate. A monolithic inductor is usually built using the top metal layers of the fabrication process in order to remove the device from the vicinity of the substrate. However, the magnetic field that is induced by the inductor has a long range compared with a typical process cross-section. This causes the inductor magnetic field to extend into the substrate. The magnetic field coupling with the substrate generates eddy currents in the substrate and degrades the monolithic inductor quality factor by increasing the inductor losses.
Optimization of the monolithic inductor for use in circuits requires maximizing the quality factor and minimizing the noise pickup from the substrate.
One technique used for reducing the capacitive coupling aspect of an inductor is shown in U.S. Pat. No. 6,133,079. This uses a P-well within an N-well, with the wells left floating.